High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. One way of achieving high data reliability is by introducing fuse arrays including a plurality of fuse sets and a plurality of redundancy decoders corresponding to the plurality of fuse sets to provide substitute rows/columns of memory cells for defective rows/columns of cells in a memory array. Each fuse set may store an address of a defective cell (Defective Address). Each redundant address decoder receives row/column address signals and compares the received row/column address signals to the defective addresses stored in the fuses. If the received row/column address signals correspond with a defective address stored in any fuse, access to the received row/column address is disabled and the redundant row/column address may be accessed instead. Defective addresses may be obtained and loaded by a plurality of tests, such as a Front End (FE) test in a manufacturing process and a Post Package Repair (PPR)/Back End (BE) test in a packaging process.
Each redundancy decoder may include a pointer (e.g., a flip-flop circuit) which enables its fuse loading. Flip-flop circuits of the plurality of redundancy decoders are coupled in a series, such as in a daisy chain. A location of the pointer in the daisy chain is shifted by every clock cycle and the address for each fuse set may be transmitted by every clock cycle. In this daisy chain configuration, relationships between pointers and corresponding fuse arrays during fuse loading are fixed based on a data structure of fuse arrays and a pointer structure.